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SoC Performance & Power Modeling at Arm

Pre-silicon perf/power analysis for next-generation heterogeneous SoCs.

ongoing

What this is

I’m a Performance and Power Engineer on the SoC Architecture Performance team at Arm in San Diego. The work is pre-silicon — quantifying latency, throughput, energy, and area impacts of compute subsystems across the hardware/software stack so architectural trade-offs can be made before there’s any silicon to measure.

The shape of the work

  • Workload characterization with hardware counters and custom telemetry.
  • Building and maintaining performance evaluation and automation frameworks in Python and C++.
  • Integrating performance data into CI for regression detection.
  • Communicating performance insights to architecture, microarchitecture, and systems teams to influence product roadmaps.

A note on detail

This page is intentionally light. I won’t share internal Arm specifics, roadmaps, customer-aligned numbers, or anything that wouldn’t pass public-disclosure review. If you’re a fellow performance engineer or SoC architect interested in talking shop within those bounds — say hi on the contact page.